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45 lines
566 B
Text
45 lines
566 B
Text
[options]
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mode bmc
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depth 1
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[engines]
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smtbmc
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[script]
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read_verilog -icells -formal test.v
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prep -top top
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[file test.v]
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module top;
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wire [7:0] a = $anyconst, b = $anyconst, fdiv, fmod, a2;
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assign a2 = b * fdiv + fmod;
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\$divfloor #(
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.A_WIDTH(8),
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.B_WIDTH(8),
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.A_SIGNED(1),
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.B_SIGNED(1),
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.Y_WIDTH(8),
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) fdiv_m (
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.A(a),
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.B(b),
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.Y(fdiv)
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);
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\$modfloor #(
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.A_WIDTH(8),
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.B_WIDTH(8),
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.A_SIGNED(1),
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.B_SIGNED(1),
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.Y_WIDTH(8),
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) fmod_m (
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.A(a),
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.B(b),
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.Y(fmod)
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);
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always @* begin
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assume(b != 0);
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assert(a == a2);
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end
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endmodule
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