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8da6f07cb3
Organize tests into subdirectories and use a new makefile that scans .sby files and allows selecting tests by mode, engine, solver and/or subdirectory. Automatically skips tests that use engines/solvers that are not found in the PATH. See `cd tests; make help` for a description of supported make targets.
25 lines
441 B
Verilog
25 lines
441 B
Verilog
module test(
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input clk,
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input [7:0] data
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);
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localparam MAX_COUNT = 8'd111;
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reg [7:0] count = 8'd0;
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reg [7:0] margin = MAX_COUNT;
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always @ (posedge clk) begin
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if (data > margin) begin
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count <= 8'd0;
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margin <= MAX_COUNT;
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end else begin
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count <= count + data;
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margin <= margin - data;
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end
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assume (data < 8'd40);
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assert (count <= MAX_COUNT);
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cover (count == 8'd42);
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cover (count == 8'd111);
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end
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endmodule
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