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911ae02ee5
Cover properties shouldn't be marked fail when the test failed early due to an assertion. This should fail without other changes.
16 lines
346 B
Verilog
16 lines
346 B
Verilog
module test (input CP, CN, input A, B, output reg XP, XN);
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reg [7:0] counter = 0;
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always @* begin
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assume (A || B);
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assume (!A || !B);
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assert (A == B);
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cover (counter == 3 && A);
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cover (counter == 3 && B);
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end
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always @(posedge CP)
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counter <= counter + 1;
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always @(posedge CP)
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XP <= A;
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always @(negedge CN)
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XN <= B;
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endmodule
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