mirror of
https://github.com/YosysHQ/sby.git
synced 2025-11-04 06:39:11 +00:00
911ae02ee5
Cover properties shouldn't be marked fail when the test failed early due to an assertion. This should fail without other changes.
16 lines
346 B
Verilog
16 lines
346 B
Verilog
module test (input CP, CN, input A, B, output reg XP, XN);
|
|
reg [7:0] counter = 0;
|
|
always @* begin
|
|
assume (A || B);
|
|
assume (!A || !B);
|
|
assert (A == B);
|
|
cover (counter == 3 && A);
|
|
cover (counter == 3 && B);
|
|
end
|
|
always @(posedge CP)
|
|
counter <= counter + 1;
|
|
always @(posedge CP)
|
|
XP <= A;
|
|
always @(negedge CN)
|
|
XN <= B;
|
|
endmodule
|