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62 lines
1.3 KiB
Text
62 lines
1.3 KiB
Text
[options]
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mode bmc
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depth 1
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expect error
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[engines]
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smtbmc
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[script]
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read_rtlil test.il
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cutpoint -blackbox
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[file test.il]
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autoidx 31
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attribute \keep 1
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attribute \top 1
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attribute \library "work"
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attribute \hdlname "top"
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module \top
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wire $auto$rtlil.cc:2739:Not$26
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wire $auto$rtlil.cc:2739:Not$28
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wire width 8 $verific$n12$4
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attribute \anyconst 1
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wire width 8 \a
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wire width 8 \b
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cell $assert $auto$verificsva.cc:1732:import$24
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connect \A $auto$rtlil.cc:2739:Not$28
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connect \EN $auto$rtlil.cc:2739:Not$26
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end
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cell $not $auto$verificsva.cc:1745:import$25
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $auto$rtlil.cc:2739:Not$28
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connect \Y $auto$rtlil.cc:2739:Not$26
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end
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cell $anyconst $verific$a$test.v:8$2
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parameter \WIDTH 8
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connect \Y \a
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end
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cell $eq $verific$equal_4$test.v:17$22
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parameter \A_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_SIGNED 0
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 1
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connect \A $verific$n12$4
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connect \B \b
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connect \Y $auto$rtlil.cc:2739:Not$28
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end
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cell $not $verific$inv_3$test.v:17$21
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parameter \A_SIGNED 0
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parameter \A_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A \a
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connect \Y $verific$n12$4
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end
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cell \submod \submod
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connect \a \a
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connect \b \b
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end
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end
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