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Miodrag Milanović 93d65cc865
Merge pull request #115 from nakengelhardt/rename_test 
rename make test to make ci
2020-09-11 16:28:32 +02:00
docs Improvements in "make test" 2020-07-24 14:58:23 +02:00
extern Include verilog source files for demo1.sby 2020-07-21 13:01:36 +02:00
sbysrc Add a PROGRAM_PREFIX= Makefile option for packages with prefixed Yosys. 2020-08-22 14:45:47 +00:00
tests fix test rule 2020-07-24 16:06:44 +02:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
COPYING Adding top level COPYING file. 2019-04-11 15:32:32 -07:00
Makefile rename make test to make ci 2020-09-11 13:22:07 +02:00
README.md Adding license info to the top level README file too. 2019-04-11 15:36:19 -07:00

README.md

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See http://symbiyosys.readthedocs.io/ for documentation on how to use SymbiYosys.

Many example designs using SymbiYosys have been published on the ZipCPU blog. Please consider browsing the formal verification page of the ZipCPU blog for examples and commentary.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.