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61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
module testbench (
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input clk, wen,
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input [9:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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memory uut (
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.clk (clk ),
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.wen (wen ),
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.addr (addr ),
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.wdata(wdata),
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.rdata(rdata)
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);
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wire [9:0] test_addr = $anyconst;
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reg test_data_valid = 0;
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reg [7:0] test_data;
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always @(posedge clk) begin
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if (addr == test_addr) begin
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if (wen) begin
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test_data <= wdata;
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test_data_valid <= 1;
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end
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if (test_data_valid) begin
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assert(test_data == rdata);
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end
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end
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end
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endmodule
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module memory (
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input clk, wen,
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input [9:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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reg [7:0] bank0 [0:255];
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reg [7:0] bank1 [0:255];
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reg [7:0] bank2 [0:255];
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reg [7:0] bank3 [0:255];
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wire [1:0] mem_sel = addr[9:8];
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wire [7:0] mem_addr = addr[7:0];
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always @(posedge clk) begin
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case (mem_sel)
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0: if (wen) bank0[mem_addr] <= wdata;
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1: if (wen) bank1[mem_addr] <= wdata;
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2: if (wen) bank1[mem_addr] <= wdata; // BUG: Should assign to bank2
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3: if (wen) bank3[mem_addr] <= wdata;
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endcase
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end
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assign rdata =
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mem_sel == 0 ? bank0[mem_addr] :
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mem_sel == 1 ? bank1[mem_addr] :
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mem_sel == 2 ? bank2[mem_addr] :
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mem_sel == 3 ? bank3[mem_addr] : 'bx;
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endmodule
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