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23 lines
276 B
Plaintext
23 lines
276 B
Plaintext
[tasks]
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btormc
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yices
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[options]
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mode bmc
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yices: expect error
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btormc: expect pass
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[engines]
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btormc: btor btormc
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yices: smtbmc yices
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[script]
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read_verilog -sv test.sv
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prep -top test
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[file test.sv]
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module test(input foo);
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always @* assume(0);
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always @* assert(foo);
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endmodule
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