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18 lines
320 B
Verilog
18 lines
320 B
Verilog
module test (input CP, CN, CX, input A, B, output reg XP, XN, YP, YN);
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always @* begin
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assume (A || B);
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assume (!A || !B);
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assert (A != B);
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cover (A);
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cover (B);
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end
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always @(posedge CP)
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XP <= A;
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always @(negedge CN)
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XN <= B;
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always @(posedge CX)
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YP <= A;
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always @(negedge CX)
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YN <= B;
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endmodule
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