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16 lines
426 B
Systemverilog
16 lines
426 B
Systemverilog
module demo_props (
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input clock, reset,
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input A, B, C, D
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);
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default clocking @(posedge clock); endclocking
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default disable iff (reset);
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assert property (A |-> !{B,C,D} [*] ##1 B);
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assert property (B |-> !{A,C,D} [*] ##1 C);
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assert property (C |-> !{A,B,D} [*] ##1 D);
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assert property (D |-> !{A,B,C} [*] ##1 A);
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cover property (A ##[+] B ##[+] C ##[+] D ##[+] A);
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endmodule
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bind demo demo_props demo_props_i (.*);
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