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19 lines
858 B
Systemverilog
19 lines
858 B
Systemverilog
module demo_counter_abstr (
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input clock, reset,
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input [19:0] counter
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);
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default clocking @(posedge clock); endclocking
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default disable iff (reset);
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// make sure the counter doesn't jump over any of the "magic values"
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`demo_counter_abstr_mode property ((counter < 123456) |=> (counter <= 123456));
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`demo_counter_abstr_mode property ((counter < 234567) |=> (counter <= 234567));
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`demo_counter_abstr_mode property ((counter < 345678) |=> (counter <= 345678));
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`demo_counter_abstr_mode property ((counter < 456789) |=> (counter <= 456789));
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// strictly increasing, only allow overflow by visiting the max value
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`demo_counter_abstr_mode property (counter != 20'hfffff |=> $past(counter) < counter);
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`demo_counter_abstr_mode property (counter == 20'hfffff |=> counter == 20'h00000);
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endmodule
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bind demo demo_counter_abstr demo_counter_abstr_i (.*);
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