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Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.
20 lines
226 B
Text
20 lines
226 B
Text
[tasks]
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bmc
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cover
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[options]
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bmc: mode bmc
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cover: mode cover
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depth 16
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[engines]
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smtbmc bitwuzla
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[script]
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verific -vhdl updowncount.vhd
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verific -sv formal_bind.sv
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prep -top updowncount
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[files]
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updowncount.vhd
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formal_bind.sv
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