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32 lines
337 B
Plaintext
32 lines
337 B
Plaintext
[options]
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mode bmc
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depth 1
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expect error
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[engines]
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smtbmc
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[script]
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read_verilog -formal test.v
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prep -top top
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[file test.v]
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(* blackbox *)
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module submod(a, b);
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input [7:0] a;
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output [7:0] b;
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endmodule
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module top;
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wire [7:0] a = $anyconst, b;
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submod submod(
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.a(a),
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.b(b)
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);
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always @* begin
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assert(~a == b);
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end
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endmodule
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