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The goal of this is to make sure that all backend flows are compatible and we can map between them, so that e.g. the aiger model can be used to minimize a counterexample trace produced by smtbmc. Reducing the parts that differ per backend (including parts that receive different input depending on the used backend) also makes testing more effective as the common parts are easier to cover.
17 lines
346 B
Verilog
17 lines
346 B
Verilog
module test (input CP, CN, input A, B, output reg XP, XN);
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reg [7:0] counter = 0;
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always @* begin
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assume (A || B);
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assume (!A || !B);
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assert (A != B);
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cover (counter == 3 && A);
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cover (counter == 3 && B);
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end
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always @(posedge CP)
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counter <= counter + 1;
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always @(posedge CP)
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XP <= A;
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always @(negedge CN)
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XN <= B;
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endmodule
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