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11 lines
227 B
Verilog
11 lines
227 B
Verilog
module primegen;
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wire [31:0] prime = $anyconst;
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wire [15:0] factor = $allconst;
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always @* begin
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if (1 < factor && factor < prime)
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assume((prime % factor) != 0);
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assume(prime > 1000000000);
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cover(1);
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end
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endmodule
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