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17 lines
274 B
Systemverilog
17 lines
274 B
Systemverilog
module top (
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input clk,
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input [7:0] din
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);
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reg [31:0] state = 0;
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always @(posedge clk) begin
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state <= ((state << 5) + state) ^ din;
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end
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`ifdef FORMAL
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always @(posedge clk) begin
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cover (state == 'd 12345678);
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cover (state == 'h 12345678);
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end
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`endif
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endmodule
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