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63 lines
994 B
Systemverilog
63 lines
994 B
Systemverilog
module fib (
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input clk, pause, start,
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input [3:0] n,
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output reg busy, done,
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output reg [9:0] f
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);
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reg [3:0] count;
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reg [9:0] q;
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initial begin
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done = 0;
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busy = 0;
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end
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always @(posedge clk) begin
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done <= 0;
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if (!pause) begin
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if (!busy) begin
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if (start)
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busy <= 1;
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count <= 0;
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q <= 1;
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f <= 0;
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end else begin
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q <= f;
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f <= f + q;
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count <= count + 1;
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if (count == n) begin
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busy <= 0;
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done <= 1;
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end
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end
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end
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end
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`ifdef FORMAL
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always @(posedge clk) begin
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if (busy) begin
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assume (!start);
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assume ($stable(n));
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end
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if (done) begin
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case ($past(n))
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0: assert (f == 1);
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1: assert (f == 1);
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2: assert (f == 2);
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3: assert (f == 3);
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4: assert (f == 5);
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5: assert (f == 8);
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endcase
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cover (f == 13);
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cover (f == 144);
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cover ($past(n) == 15);
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end
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assume property (s_eventually !pause);
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if (start && !pause)
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assert property (s_eventually done);
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end
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`endif
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endmodule
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