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sby/docs/examples/vhd
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Krystine Sherwin 549c5f33f5
Add formal_bind example 
Demonstrate binding SVA properties to a VHDL design.
Mention example code (with snippets) in section on Verific.
2024-03-05 15:29:08 +13:00
..
.gitignore Add formal_bind example 2024-03-05 15:29:08 +13:00
formal_bind.sby Add formal_bind example 2024-03-05 15:29:08 +13:00
formal_bind.sv Add formal_bind example 2024-03-05 15:29:08 +13:00
updowncount.vhd Add formal_bind example 2024-03-05 15:29:08 +13:00