Krystine Sherwin 27e20fd5c3 Add sphinx-argparse to generate usage ... Move parser generation into a seperate file to avoid import issues with bad python modules during docs gen. With the requirements.txt provided to readthedocs, there shouldn't need to be any other changes? Also I've never been able to run `make test` so I'm not actually sure if the changes break sby, but they shouldn't.		2023-06-13 11:40:28 +12:00
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sby.py	Add sphinx-argparse to generate usage	2023-06-13 11:40:28 +12:00
sby_autotune.py	Run tasks in parallel	2022-08-18 14:38:40 +02:00
sby_cmdline.py	Add sphinx-argparse to generate usage	2023-06-13 11:40:28 +12:00
sby_core.py	Add aigvmap and aigsyms options	2023-06-03 22:16:35 +02:00
sby_design.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_abc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_aiger.py	avy: Fold aiger model using abc to support assumptions	2023-01-11 18:36:06 +01:00
sby_engine_btor.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_engine_smtbmc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_jobserver.py	Support "fifo:" make jobserver auth	2023-01-10 18:42:26 +01:00
sby_mode_bmc.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_mode_cover.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_mode_live.py	Add colors to engine header message	2022-11-24 18:12:22 +01:00
sby_mode_prove.py	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
sby_sim.py	Enable yosys sim support for clock signals in hierarchical designs	2023-01-11 18:02:45 +01:00