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19 lines
330 B
Verilog
19 lines
330 B
Verilog
module demo (
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input clock,
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input reset,
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output A, B, C, D
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);
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reg [19:0] counter = 0;
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always @(posedge clock) begin
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if (reset)
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counter <= 0;
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else
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counter <= counter + 20'd 1;
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end
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assign A = counter == 123456;
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assign B = counter == 234567;
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assign C = counter == 345678;
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assign D = counter == 456789;
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endmodule
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