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fedfae0e9c
The $stable value change expression cannot be true for a non-x signal in the initial state. This is now correctly handled by the verific import, so the dpmem example needs to start assuming `$stable` only after leaving the initial state.
66 lines
1 KiB
Systemverilog
66 lines
1 KiB
Systemverilog
module dpmem (
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input rc,
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input [3:0] ra,
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output reg [3:0] rd,
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input wc,
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input we,
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input [3:0] wa,
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input [3:0] wd
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);
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reg [3:0] mem [0:15];
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always @(posedge rc) begin
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rd <= mem[ra];
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end
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always @(posedge wc) begin
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if (we) mem[wa] <= wd;
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end
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endmodule
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module top (
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input rc,
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input [3:0] ra,
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output [3:0] rd,
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input wc,
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input we,
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input [3:0] wa,
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input [3:0] wd
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);
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dpmem uut (
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.rc(rc),
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.ra(ra),
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.rd(rd),
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.wc(wc),
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.we(we),
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.wa(wa),
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.wd(wd)
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);
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reg shadow_valid = 0;
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reg [3:0] shadow_data;
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(* anyconst *) reg [3:0] shadow_addr;
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reg init = 1;
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(* gclk *) reg gclk;
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always @(posedge gclk) begin
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if (!init) begin
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assume ($stable(rc) || $stable(wc));
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if ($rose(rc) && shadow_valid && shadow_addr == $past(ra)) begin
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assert (shadow_data == rd);
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end
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if ($rose(wc) && $past(we) && shadow_addr == $past(wa)) begin
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shadow_data <= $past(wd);
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shadow_valid <= 1;
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end
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end
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init <= 0;
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end
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endmodule
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