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58 lines
1.2 KiB
Verilog
58 lines
1.2 KiB
Verilog
module testbench (
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input clk, wen,
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input [15:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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memory uut (
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.clk (clk ),
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.wen (wen ),
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.addr (addr ),
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.wdata(wdata),
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.rdata(rdata)
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);
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wire [15:0] test_addr = $anyconst;
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reg test_data_valid = 0;
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reg [7:0] test_data;
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always @(posedge clk) begin
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if (addr == test_addr) begin
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if (wen) begin
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test_data <= wdata;
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test_data_valid <= 1;
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end
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if (test_data_valid) begin
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assert(test_data == rdata);
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end
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end
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end
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endmodule
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module memory (
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input clk, wen,
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input [15:0] addr,
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input [7:0] wdata,
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output [7:0] rdata
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);
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reg [7:0] bank0 [0:'h3fff];
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reg [7:0] bank1 [0:'h3fff];
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reg [7:0] bank2 [0:'h3fff];
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reg [7:0] bank3 [0:'h3fff];
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always @(posedge clk) begin
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case (addr[15:14])
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0: if (wen) bank0[addr[13:0]] <= wdata;
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1: if (wen) bank1[addr[13:0]] <= wdata;
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2: if (wen) bank1[addr[13:0]] <= wdata; // BUG: Should assign to bank2
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3: if (wen) bank3[addr[13:0]] <= wdata;
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endcase
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end
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assign rdata =
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addr[15:14] == 0 ? bank0[addr[13:0]] :
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addr[15:14] == 1 ? bank1[addr[13:0]] :
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addr[15:14] == 2 ? bank2[addr[13:0]] :
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addr[15:14] == 3 ? bank3[addr[13:0]] : 'bx;
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endmodule
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