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38 lines
618 B
Plaintext
38 lines
618 B
Plaintext
[tasks]
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smtbmc mode_bmc
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btor_bmc engine_btor mode_bmc
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btor_cover engine_btor mode_cover
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abc mode_bmc
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aiger engine_aiger mode_prove
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[options]
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mode_bmc: mode bmc
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mode_prove: mode prove
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mode_cover: mode cover
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vcd off
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~mode_cover: expect fail
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[engines]
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smtbmc: smtbmc
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engine_btor: btor btormc
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abc: abc bmc3
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aiger: aiger suprove
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[script]
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read_verilog -formal no_vcd.sv
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prep -top top
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[file no_vcd.sv]
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module top(input clk, input force);
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reg [4:0] counter = 0;
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always @(posedge clk) begin
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if (!counter[4] || force)
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counter <= counter + 1;
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assert (counter < 10);
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cover (counter == 4);
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end
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endmodule
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