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50 lines
782 B
Verilog
50 lines
782 B
Verilog
module testbench (
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input clk,
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input reset,
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input [7:0] din,
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output reg [7:0] dout
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);
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demo uut (
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.clk (clk ),
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.reset(reset),
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.din (din ),
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.dout (dout ),
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);
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initial assume (reset);
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assert property (reset || !dout[1:0]);
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endmodule
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module demo (
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input clk,
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input reset,
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input [7:0] din,
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output reg [7:0] dout
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);
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reg [7:0] buffer;
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reg [2:0] state;
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always @(posedge clk) begin
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if (reset) begin
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dout <= 0;
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state <= 0;
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end else
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case (state)
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3'b 001: begin
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buffer <= din;
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state <= 1;
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end
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3'b 010: begin
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if (buffer[1:0])
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buffer <= buffer + 1;
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else
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state <= 2;
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end
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3'b 100: begin
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dout <= dout + buffer;
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state <= 0;
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end
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endcase
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end
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endmodule
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