Krystine Sherwin 549c5f33f5 Add formal_bind example ... Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.		2024-03-05 15:29:08 +13:00
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abstract	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
autotune	example for autotune	2022-07-26 16:06:02 +02:00
demos	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
dft	Add dft/data_diode example	2023-09-28 18:59:27 +02:00
fifo	tests: Do not run the same SBY task multiple times in parallel	2022-10-20 14:18:51 +02:00
indinv	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
multiclk	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
puzzles	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
quickstart	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00
tristate	add makefile for test	2022-06-14 15:35:22 +02:00
vhd	Add formal_bind example	2024-03-05 15:29:08 +13:00
Makefile	Use the test Makefile for all examples	2022-06-13 13:42:58 +02:00