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11 commits

Author SHA1 Message Date
Jannis Harder 6d3b5aa960 Unified trace generation using yosys's sim across all engines
Currently opt-in using the `fst` or `vcd_sim` options.
2023-01-10 18:42:26 +01:00
Jannis Harder 168d667b6d Add vcd option to make VCD writing optional 2022-09-05 15:42:24 +02:00
Jannis Harder 5265a52b65 Refactor flow to use a common prep model
The goal of this is to make sure that all backend flows are compatible
and we can map between them, so that e.g. the aiger model can be used to
minimize a counterexample trace produced by smtbmc. Reducing the parts
that differ per backend (including parts that receive different input
depending on the used backend) also makes testing more effective as the
common parts are easier to cover.
2022-08-05 16:31:15 +02:00
Jannis Harder e3123283ea
Merge pull request #170 from programmerjake/add-simcheck-option
switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules
2022-07-03 11:47:22 +02:00
Jacob Lifshay db740839b7 switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules.
Fixes: #168

Depends on: https://github.com/YosysHQ/yosys/pull/3391
2022-06-22 21:17:29 -07:00
Jannis Harder 05d963b0df aiger: check supported modes and aigbmc fixes 2022-06-14 17:41:06 +02:00
Jannis Harder d0da57f54f Test that cvc4 and cvc5 can be used 2022-06-08 13:33:12 +02:00
Jannis Harder b4c110815c Test designs using $allconst 2022-06-03 16:55:06 +02:00
Jacob Lifshay a87d21a802 add depth 1 2022-05-25 03:35:21 -07:00
Jacob Lifshay 3f32deb8c9 add test for yosys's $divfloor and $modfloor cells
Depends on: https://github.com/YosysHQ/yosys/pull/3335
2022-05-24 17:51:48 -07:00
Jannis Harder 8da6f07cb3 Refactor tests
Organize tests into subdirectories and use a new makefile that scans
.sby files and allows selecting tests by mode, engine, solver and/or
subdirectory. Automatically skips tests that use engines/solvers that
are not found in the PATH.

See `cd tests; make help` for a description of supported make targets.
2022-04-11 17:50:38 +02:00