Jannis Harder
b6e41a388b
Support for the new anytime schedule in yosys-abc's pdr
2024-03-06 12:26:01 +01:00
Jannis Harder
6ba762db4c
Support for "abc --keep-going pdr" via new "pdr -X" mode
2024-02-20 14:06:43 +01:00
Jannis Harder
52184e5bf0
Initial support for a multi-task property status database
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This adds initial support for an sqlite database that is shared across
multiple tasks of a single SBY file and that can track the status of
individual properties.
The amount of information tracked in the database is currently quite
minimal and depends on the engine and options used. This can be
incrementally extended in the future.
The ways in which the information in the database can be queries is even
more limited for this initial version, consisting of a single '--status'
option which lists all properties and their status.
2024-02-20 13:34:58 +01:00
Jannis Harder
1eeb6f3f0b
Delete $print cells in the backend flows
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They are only useful and supported for the simulation that is run with
the output of the prep flow, not the output of the backend flows.
2024-01-22 18:10:00 +01:00
Jannis Harder
884ef862cb
assume_early option to implement cross assumes in IVY
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Checking IVY's cross assumes requires delaying a subset of assumptions,
which we don't want SBY to undo.
2023-08-11 15:58:55 +02:00
Claire Xen
4cddd7a749
Merge branch 'master' into krys/scy_dev
2023-07-18 16:46:09 +02:00
Claire Xenia Wolf
8b3ba68845
Add aigfolds option
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-06-07 22:05:17 +02:00
Claire Xenia Wolf
7d60a3ba34
Add aigvmap and aigsyms options
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-06-03 22:16:35 +02:00
Claire Xenia Wolf
f49c9ebb29
Make call to "witness -rename" optional (default=on)
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-06-02 13:04:45 +02:00
Krystine Sherwin
36e7a72586
Adding prep mode and skip_prep option
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Allows for generating a design_prep model which can then be used by multiple distinct sby runs.
2023-05-16 17:42:53 +12:00
Jannis Harder
74f33880bd
Merge pull request #232 from dlmiles/win-qol-cleanopt
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-f clean: QoL improvement on Windows concerning file/dir removal locking
2023-02-20 19:48:36 +01:00
Darryl L. Miles
fa5bc957c1
-f clean: QoL improvement on Windows concerning file/dir removal locking
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When using the -f argument be more forgiving with the expectation of a clean
workspace and the expectation of the new sby run being responsible for
directory creation.
This is a usability and quality of life improvement for Windows users where
the OS can implement file and directory locking implicitly. In the EDA world
it is common to have multiple tools in use at any one time and it can become
tortious to have to close files / exit 3rd party applications to release
locking so sby is happy to rerun.
This change will prevent sby claiming a terminal error has occurred when it
fails to create a directory that already exists. It also now considers the
environment to be 'clean' (as per -f) if all the non-directory elements of
the file tree have been deleted, leaving potentially an empty a skeleton of
directories.
2023-02-18 09:36:18 +00:00
Jannis Harder
c5dce57067
append_assume: Make append_assume on the default for now
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Having `append_assume off` needs `vcd_sim on` to not be ignored with a
warning and `vcd_sim off` is still the default.
2023-02-08 14:18:52 +01:00
Jannis Harder
f14aaa57c4
avy: Fold aiger model using abc to support assumptions
2023-01-11 18:36:06 +01:00
Jannis Harder
6398938e6a
Enable yosys sim support for clock signals in hierarchical designs
2023-01-11 18:02:45 +01:00
Jannis Harder
6d3b5aa960
Unified trace generation using yosys's sim across all engines
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Currently opt-in using the `fst` or `vcd_sim` options.
2023-01-10 18:42:26 +01:00
Claire Xenia Wolf
e8d713cc27
Add colors to early and late log messages
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-11-02 12:35:11 +01:00
Claire Xenia Wolf
003ccf7197
Add color handling via click.style and click.echo
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-31 20:29:32 +01:00
Jannis Harder
966bdae1f6
aigbmc: Convert aiw trace to yw trace and load that into smtbmc
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This handles more edge cases concerning FF initialization, memories and
hierarchy.
2022-10-20 14:36:07 +02:00
Jannis Harder
83a1aa23c8
Merge pull request #218 from jix/fix_engine_list
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Fix engine_list's return value
2022-09-15 17:59:25 +02:00
Jannis Harder
a0e3dd3d9a
Fix engine_list's return value
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This fixes #216
2022-09-15 15:47:27 +02:00
Jannis Harder
168d667b6d
Add vcd option to make VCD writing optional
2022-09-05 15:42:24 +02:00
Jannis Harder
bd88454d7d
Merge pull request #196 from jix/parallel_jobserver
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Run tasks in parallel and integrate with the make jobserver
2022-08-19 14:21:53 +02:00
Jannis Harder
b0786aea43
Make jobserver integration
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Only implements the POSIX jobserver and will break on windows.
Unbreaking it on windows will be done as a follow up.
Not used for autotune, that needs some more changes.
2022-08-18 14:40:00 +02:00
Jannis Harder
de939e279a
Run tasks in parallel
2022-08-18 14:38:40 +02:00
Aki Van Ness
de40cc499f
sby: core: removed invalid None check in setup section
2022-08-18 05:52:38 -04:00
Aki Van Ness
41b4ce5a7e
sby: fixed issue where engine index would be out of range
2022-08-18 05:51:03 -04:00
Aki Van Ness
8f5508142d
sby: core: minor error message cleanups for consistency
2022-08-18 05:36:11 -04:00
Aki Van Ness
a6c220dd5d
docs: Cut out the in-progress docs in preperation for a merge
2022-08-18 05:36:11 -04:00
Aki Van Ness
841e0cb797
sby: core: Added unsupported messages to the new sections
2022-08-18 05:36:11 -04:00
Aki Van Ness
637095a8ec
sby: fixed the sby task execution to accept the new engine internal layout
2022-08-18 05:36:11 -04:00
Aki Van Ness
98fdcd7772
sby: core: fixed up the [setup] section
2022-08-18 05:36:11 -04:00
Aki Van Ness
6c959577f3
sby: core: cleaned up the [stage] section parsing
2022-08-18 05:36:11 -04:00
Aki Van Ness
ad4f506d2a
sby: core: fixed up the engines section parser
2022-08-18 05:36:10 -04:00
Aki Van Ness
2f841e5d55
sby: core: updated the parsing to match the changes in PR #206
2022-08-18 05:36:10 -04:00
Aki Van Ness
e4a7f624c1
sby: core: config: fixed the engines section parsing where it was not setting the engine mode when parsing the section
2022-08-18 05:36:10 -04:00
Aki Van Ness
204869bfed
sby: core: config: updated the error messages for the new setctions to make them more descriptive
2022-08-18 05:36:10 -04:00
Aki Van Ness
9293081308
modified the mode runners to accept the modified engine layout in preperation for the per-mode engine sections
2022-08-18 05:36:10 -04:00
Aki Van Ness
f1a645bb18
sby: core: config: Updated the [stage] section to use commas for the parents
2022-08-18 05:36:09 -04:00
Aki Van Ness
a0d366e58a
some cleanup, added some rough parser tests, and started altering the engines section
2022-08-18 05:36:09 -04:00
Aki Van Ness
0ab158eea1
sby: core: minor update to the stage parsing
2022-08-18 05:36:09 -04:00
Aki Van Ness
ed82c78acc
sby: core: Added preliminary support for [stage] sections
2022-08-18 05:36:08 -04:00
Aki Van Ness
4cccbf77fa
sby: core: Added preliminary support for the [setup] section
2022-08-18 05:36:08 -04:00
Jannis Harder
0aebf0b4d0
aig model: Call memory_map late to avoid performance issues
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This requires running simplemap on the output as memory_map produces
coarse-grained cells even though we already have a fine-grained design.
2022-08-17 16:41:32 +02:00
Jannis Harder
3412ea859b
New "none" engine to be used with the "make_model" option
2022-08-05 16:31:15 +02:00
Jannis Harder
231f0b80aa
Add make_model option to generate models not required by the task
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Useful to do custom things (like counter example minimization) but still
use sby's flow to prepare models.
2022-08-05 16:31:15 +02:00
Jannis Harder
22585b33dc
Use 'rename -witness' instead of multiple 'rename -enumerate'
2022-08-05 16:31:15 +02:00
Jannis Harder
d3520037b9
Write native yosys witness traces
2022-08-05 16:31:15 +02:00
Jannis Harder
acaf6ef0c2
Use new memory_map -formal for aiger/_nomem
2022-08-05 16:31:15 +02:00
Jannis Harder
5265a52b65
Refactor flow to use a common prep model
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The goal of this is to make sure that all backend flows are compatible
and we can map between them, so that e.g. the aiger model can be used to
minimize a counterexample trace produced by smtbmc. Reducing the parts
that differ per backend (including parts that receive different input
depending on the used backend) also makes testing more effective as the
common parts are easier to cover.
2022-08-05 16:31:15 +02:00
