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2 commits

Author SHA1 Message Date
Jannis Harder 6398938e6a Enable yosys sim support for clock signals in hierarchical designs 2023-01-11 18:02:45 +01:00
Jannis Harder 6d3b5aa960 Unified trace generation using yosys's sim across all engines 
Currently opt-in using the `fst` or `vcd_sim` options.
 2023-01-10 18:42:26 +01:00