10 commits

Author	SHA1	Message	Date
N. Engelhardt	9675d158ce	Merge pull request #264 from YosysHQ/krys/vhd_example ... Add formal_bind example	2025-03-03 15:20:59 +00:00
Krystine Sherwin	7f1853bd78	Add note on docs to clarify verific support ... Having a verific license does not provide access to the verific frontend. This helps to make that clearer.	2024-05-14 12:25:29 +12:00
Krystine Sherwin	549c5f33f5	Add formal_bind example ... Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.	2024-03-05 15:29:08 +13:00
Clifford Wolf	93e7e1d1e2	Improve documentation of scripts and Verific bindings ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-06-23 18:25:52 +02:00
Clifford Wolf	437a401739	Add [script] documentation, add some paragraphs on "verific" command ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-04-18 19:32:58 +02:00
Clifford Wolf	055b305c81	Update verific.rst ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 23:46:52 +01:00
Clifford Wolf	fd0fd88e22	Update verific.rst ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 15:41:57 +01:00
Clifford Wolf	f151ea733a	Update verific.rst ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 11:19:27 +01:00
Clifford Wolf	fbd5ddb615	Minor format fix in documentation ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 01:18:19 +01:00
Clifford Wolf	9e35d16e95	Add more documentation ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-06 01:12:03 +01:00