mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-04 05:49:57 +00:00
Code Activity

aig model: Call memory_map late to avoid performance issues

Browse source 
This requires running simplemap on the output as memory_map produces
coarse-grained cells even though we already have a fine-grained design.
This commit is contained in:
Jannis Harder 2022-08-08 14:25:48 +02:00
parent 3412ea859b
commit fdb6e8d838
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
sbysrc/sby_core.py
View file

@ -726,8 +726,6 @@ class SbyTask(SbyConfig):
print(f"# running in {self.workdir}/model/", file=f)
print("read_ilang design_prep.il", file=f)
print("hierarchy -simcheck", file=f)
print("memory_map -formal", file=f)
print("formalff -setundef -clk2ff -ff2anyinit", file=f)
print("flatten", file=f)
print("setundef -undriven -anyseq", file=f)
print("setattr -unset keep", file=f)
@ -735,6 +733,9 @@ class SbyTask(SbyConfig):
print("opt -full", file=f)
print("techmap", file=f)
print("opt -fast", file=f)
print("memory_map -formal", file=f)
print("formalff -clk2ff -ff2anyinit", file=f)
print("simplemap", file=f)
print("dffunmap", file=f)
print("abc -g AND -fast", file=f)
print("opt_clean", file=f)