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docs/examples/indinv/README.md
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@ -17,9 +17,12 @@ the following technique for proving and using inductive invariants.
Consider the following circuit (stripped-down [example.sv](example.sv)): Consider the following circuit (stripped-down [example.sv](example.sv)):
```SystemVerilog ```SystemVerilog
module example(input logic clk, output reg [4:0] state); module example(clk, state);
initial state = 27; input logic clk;
output logic [4:0] state = 27;
always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7); always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7);
always_comb assert (state != 0); always_comb assert (state != 0);
endmodule endmodule
``` ```