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Clifford Wolf 2017-01-29 17:14:05 +01:00
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@ -7,16 +7,14 @@ hardware verification flows. SymbiYosys provides flows for the following
formal tasks: formal tasks:
* Bounded verification of safety properties (assertions) * Bounded verification of safety properties (assertions)
* *Unbounded verification of safety properties* * Unbounded verification of safety properties [TBD]
* *Generation of test benches from cover statements* * Generation of test benches from cover statements [TBD]
* *Verification of liveness properties* * Verification of liveness properties [TBD]
* *Formal equivalence checking* * Formal equivalence checking [TBD]
(Italic items are features under construction and not available (Items marked [TBD] are features under construction and not available
at the moment.) at the moment.)
Contents:
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2