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switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules.

Fixes: #168

Depends on: https://github.com/YosysHQ/yosys/pull/3391
This commit is contained in:
Jacob Lifshay 2022-06-22 21:17:29 -07:00
parent 41cd8e5b5e
commit db740839b7
3 changed files with 69 additions and 6 deletions

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[options]
mode bmc
depth 1
expect error
[engines]
smtbmc
[script]
read_verilog -formal test.v
prep -top top
[file test.v]
(* blackbox *)
module submod(a, b);
input [7:0] a;
output [7:0] b;
endmodule
module top;
wire [7:0] a = $anyconst, b;
submod submod(
.a(a),
.b(b)
);
always @* begin
assert(~a == b);
end
endmodule

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[options]
mode bmc
depth 1
[engines]
smtbmc
[script]
read_verilog -formal test.v
prep -top top
[file test.v]
(* blackbox *)
(* smtlib2_module *)
module submod(a, b);
input [7:0] a;
(* smtlib2_comb_expr = "(bvnot a)" *)
output [7:0] b;
endmodule
module top;
wire [7:0] a = $anyconst, b;
submod submod(
.a(a),
.b(b)
);
always @* begin
assert(~a == b);
end
endmodule