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Support rIC3 as backend

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Signed-off-by: Yuheng Su <gipsyh.icu@gmail.com>
This commit is contained in:
Yuheng Su 2024-12-16 11:02:45 +00:00
parent 26b387466d
commit daf4e4cb39
6 changed files with 19 additions and 1 deletions
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2
docs/examples/demos/up_down_counter.sby
View file

@ -1,6 +1,7 @@
[tasks]
suprove
avy
rIC3
[options]
mode prove
@ -8,6 +9,7 @@ mode prove
[engines]
suprove: aiger suprove
avy: aiger avy
rIC3: aiger rIC3
[script]
read_verilog -formal demo.v

4
docs/source/install.rst
View file

@ -133,3 +133,7 @@ super_prove
Avy
^^^
https://arieg.bitbucket.io/avy/
rIC3
^^^^
https://github.com/gipsyh/rIC3/

4
docs/source/reference.rst
View file

@ -248,6 +248,8 @@ The following mode/engine/solver combinations are currently supported:
| | |
| | ``aiger avy`` |
| | |
| | ``aiger rIC3`` |
| | |
| | ``aiger suprove`` |
+-----------+--------------------------+
| ``cover`` | ``smtbmc [all solvers]`` |
@ -341,6 +343,8 @@ solvers:
+-------------------------------+---------------------------------+
| ``avy`` | ``prove`` |
+-------------------------------+---------------------------------+
| ``rIC3`` | ``prove`` |
+-------------------------------+---------------------------------+
| ``aigbmc`` | ``bmc`` |
+-------------------------------+---------------------------------+