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Changes to reset
Active high. Removed init. Better over/underfill cover properties for verific. Moved basic cover statement to only be used when there is no verific. Other general tidy up. Also updated/fixed a couple minor things in newstart.rst.
This commit is contained in:
KrystalDelusion
parent
a76286ed34
commit
cfa4352bae
3 changed files with 97 additions and 109 deletions
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@ -1,32 +1,36 @@
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// address generator/counter
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module addr_gen
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#( parameter MAX_DATA=16
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) ( input en, clk, rst_n,
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) ( input en, clk, rst,
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output reg [3:0] addr
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);
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initial addr <= 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or negedge rst_n)
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if (~rst_n)
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always @(posedge clk or posedge rst)
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if (rst)
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addr <= 0;
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else if (en)
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else if (en) begin
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if (addr == MAX_DATA-1)
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule
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// Define our top level fifo entity
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module fifo
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#( parameter MAX_DATA=16
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) ( input wen, ren, clk, rst_n,
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) ( input wen, ren, clk, rst,
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input [7:0] wdata,
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output [7:0] rdata,
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output [4:0] count,
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output full, empty
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);
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wire wskip, rskip;
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reg [4:0] data_count;
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// fifo storage
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// async read, sync write
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wire [3:0] waddr, raddr;
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@ -42,7 +46,7 @@ module fifo
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fifo_writer (
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.en (wen || wskip),
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.clk (clk ),
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.rst_n (rst_n),
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.rst (rst),
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.addr (waddr)
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);
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@ -50,16 +54,15 @@ module fifo
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fifo_reader (
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.en (ren || rskip),
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.clk (clk ),
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.rst_n (rst_n),
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.rst (rst),
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.addr (raddr)
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);
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// status signals
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reg [4:0] data_count;
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initial data_count <= 0;
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n)
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always @(posedge clk or posedge rst) begin
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if (rst)
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data_count <= 0;
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else if (wen && !ren && data_count < MAX_DATA)
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data_count <= data_count + 1;
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@ -68,11 +71,10 @@ module fifo
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end
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assign full = data_count == MAX_DATA;
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assign empty = (data_count == 0) && rst_n;
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assign empty = (data_count == 0) && ~rst;
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assign count = data_count;
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// overflow protection
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wire wskip, rskip;
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`ifndef NO_FULL_SKIP
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// write while full => overwrite oldest data, move read pointer
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assign rskip = wen && !ren && data_count >= MAX_DATA;
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@ -90,19 +92,10 @@ module fifo
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? waddr - raddr
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: waddr + MAX_DATA - raddr;
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reg init = 0;
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always @(posedge clk) begin
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if (rst_n)
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init <= 1;
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// if init is low we don't care about the value of rst_n
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// if init is high (rst_n has ben high), then rst_n must remain high
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assume (!init || rst_n);
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end
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// tests
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always @(posedge clk) begin
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if (rst_n) begin
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// waddr and raddr can only be non zero if reset is high
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if (~rst) begin
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// waddr and raddr can only be non zero if reset is low
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w_nreset: cover (waddr || raddr);
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// count never more than max
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@ -132,49 +125,44 @@ module fifo
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w_full: cover (wen && !ren && count == MAX_DATA-1);
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a_empty: assert (!empty || count == 0);
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w_empty: cover (ren && !wen && count == 1);
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// can we corrupt our data?
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w_overfill: cover ($past(rskip) && raddr);
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w_underfill: cover ($past(wskip) && waddr);
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end else begin
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// waddr and raddr are zero while reset is low
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a_reset: assert (!waddr && !raddr);
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w_reset: cover (~rst_n);
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// outputs are zero while reset is low
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// reading/writing non zero values
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w_nzero_write: cover (wen && wdata);
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w_nzero_read: cover (ren && rdata);
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end else begin
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// waddr and raddr are zero while reset is high
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a_reset: assert (!waddr && !raddr);
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w_reset: cover (rst);
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// outputs are zero while reset is high
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a_zero_out: assert (!empty && !full && !count);
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end
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end
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`ifdef VERIFIC
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// if we have verific we can also do the following additional tests
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always @(posedge clk) begin
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if (rst_n) begin
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// read/write enables enable
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ap_raddr2: assert property (ren |=> $changed(raddr));
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ap_waddr2: assert property (wen |=> $changed(waddr));
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// read/write enables enable
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ap_raddr2: assert property (@(posedge clk) disable iff (rst) ren |=> $changed(raddr));
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ap_waddr2: assert property (@(posedge clk) disable iff (rst) wen |=> $changed(waddr));
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// read/write needs enable UNLESS full/empty
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ap_raddr3: assert property (!ren && !full |=> $stable(raddr));
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ap_waddr3: assert property (!wen && !empty |=> $stable(waddr));
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// can we corrupt our data?
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// these should already be covered by ap_{r,w}addr2
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ap_overfill: assert property (wen && full |=> $changed(raddr));
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ap_underfill: assert property (ren && empty |=> $changed(waddr));
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// change data when writing (and only when writing) so we can line
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// up reads with writes
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//TODO: this but with a cover statement
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// assume property (wen |=> $changed(wdata));
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// assume property (!wen |=> $stable(wdata));
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end
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end
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// read/write needs enable UNLESS full/empty
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ap_raddr3: assert property (@(posedge clk) disable iff (rst) !ren && !full |=> $stable(raddr));
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ap_waddr3: assert property (@(posedge clk) disable iff (rst) !wen && !empty |=> $stable(waddr));
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// can we corrupt our data?
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w_underfill: cover property (@(posedge clk) disable iff (rst) !wen |=> $changed(waddr));
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// look for an overfill where the value in memory changes
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let d_change = (wdata != rdata);
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w_overfill: cover property (@(posedge clk) disable iff (rst) !ren && d_change |=> $changed(raddr));
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`else // !VERIFIC
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// without verific we are more limited in describing the above assumption
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always @(posedge clk) begin
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assume ((wen && wdata != $past(wdata))
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|| (!wen && wdata == $past(wdata)));
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if (~rst) begin
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// this is less reliable because $past() can sometimes give false
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// positives in the first cycle
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w_overfill: cover ($past(rskip) && raddr);
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w_underfill: cover ($past(wskip) && waddr);
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end
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end
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`endif // VERIFIC
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@ -2,33 +2,37 @@
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module addr_gen
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#( parameter MAX_DATA=16,
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parameter ADDR_BITS=5
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) ( input en, clk, rst_n,
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) ( input en, clk, rst,
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output reg [ADDR_BITS-1:0] addr
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);
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initial addr <= 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or negedge rst_n)
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if (~rst_n)
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always @(posedge clk or posedge rst)
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if (rst)
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addr <= 0;
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else if (en)
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else if (en) begin
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if (addr == MAX_DATA-1)
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule
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// Define our top level fifo entity
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module fifo
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#( parameter MAX_DATA=16,
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parameter ADDR_BITS=5
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) ( input wen, ren, clk, rst_n,
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) ( input wen, ren, clk, rst,
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input [7:0] wdata,
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output [7:0] rdata,
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output [ADDR_BITS:0] count,
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output full, empty
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);
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wire wskip, rskip;
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reg [ADDR_BITS:0] data_count;
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// fifo storage
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// async read, sync write
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wire [ADDR_BITS-1:0] waddr, raddr;
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@ -44,7 +48,7 @@ module fifo
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fifo_writer (
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.en (wen || wskip),
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.clk (clk ),
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.rst_n (rst_n),
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.rst (rst),
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.addr (waddr)
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);
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@ -52,16 +56,15 @@ module fifo
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fifo_reader (
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.en (ren || rskip),
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.clk (clk ),
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.rst_n (rst_n),
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.rst (rst),
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.addr (raddr)
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);
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// status signals
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reg [ADDR_BITS:0] data_count;
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initial data_count <= 0;
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n)
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always @(posedge clk or posedge rst) begin
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if (rst)
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data_count <= 0;
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else if (wen && !ren && data_count < MAX_DATA)
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data_count <= data_count + 1;
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@ -70,11 +73,10 @@ module fifo
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end
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assign full = data_count == MAX_DATA;
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assign empty = (data_count == 0) && rst_n;
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assign empty = (data_count == 0) && ~rst;
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assign count = data_count;
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// overflow protection
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wire wskip, rskip;
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`ifndef NO_FULL_SKIP
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// write while full => overwrite oldest data, move read pointer
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assign rskip = wen && !ren && data_count >= MAX_DATA;
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@ -89,22 +91,13 @@ module fifo
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// observers
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wire [ADDR_BITS:0] addr_diff;
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assign addr_diff = waddr >= raddr
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? waddr - raddr
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: waddr + MAX_DATA - raddr;
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reg init = 0;
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always @(posedge clk) begin
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if (rst_n)
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init <= 1;
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// if init is low we don't care about the value of rst_n
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// if init is high (rst_n has ben high), then rst_n must remain high
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assume (!init || rst_n);
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end
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? waddr - raddr
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: waddr + MAX_DATA - raddr;
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// tests
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always @(posedge clk) begin
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if (rst_n) begin
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// waddr and raddr can only be non zero if reset is high
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if (~rst) begin
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// waddr and raddr can only be non zero if reset is low
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w_nreset: cover (waddr || raddr);
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// count never more than max
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@ -134,35 +127,43 @@ module fifo
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w_full: cover (wen && !ren && count == MAX_DATA-1);
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a_empty: assert (!empty || count == 0);
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w_empty: cover (ren && !wen && count == 1);
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// can we corrupt our data?
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w_overfill: cover ($past(rskip) && raddr);
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w_underfill: cover ($past(wskip) && waddr);
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end else begin
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// waddr and raddr are zero while reset is low
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a_reset: assert (!waddr && !raddr);
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w_reset: cover (~rst_n);
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// outputs are zero while reset is low
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// reading/writing non zero values
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w_nzero_write: cover (wen && wdata);
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w_nzero_read: cover (ren && rdata);
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end else begin
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// waddr and raddr are zero while reset is high
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a_reset: assert (!waddr && !raddr);
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w_reset: cover (rst);
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// outputs are zero while reset is high
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a_zero_out: assert (!empty && !full && !count);
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end
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end
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`ifdef VERIFIC
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// if we have verific we can also do the following additional tests
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always @(posedge clk) begin
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if (rst_n) begin
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// read/write enables enable
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ap_raddr2: assert property (ren |=> $changed(raddr));
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ap_waddr2: assert property (wen |=> $changed(waddr));
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// read/write enables enable
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ap_raddr2: assert property (@(posedge clk) disable iff (rst) ren |=> $changed(raddr));
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ap_waddr2: assert property (@(posedge clk) disable iff (rst) wen |=> $changed(waddr));
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// read/write needs enable UNLESS full/empty
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ap_raddr3: assert property (@(posedge clk) disable iff (rst) !ren && !full |=> $stable(raddr));
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ap_waddr3: assert property (@(posedge clk) disable iff (rst) !wen && !empty |=> $stable(waddr));
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// can we corrupt our data?
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w_underfill: cover property (@(posedge clk) disable iff (rst) !wen |=> $changed(waddr));
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// look for an overfill where the value in memory changes
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let d_change = (wdata != rdata);
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w_overfill: cover property (@(posedge clk) disable iff (rst) !ren && d_change |=> $changed(raddr));
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`else // !VERIFIC
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always @(posedge clk) begin
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if (~rst) begin
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// this is less reliable because $past() can sometimes give false
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// positives in the first cycle
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w_overfill: cover ($past(rskip) && raddr);
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w_underfill: cover ($past(wskip) && waddr);
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// read/write needs enable UNLESS full/empty
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ap_raddr3: assert property (!ren && !full |=> $stable(raddr));
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ap_waddr3: assert property (!wen && !empty |=> $stable(waddr));
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// can we corrupt our data?
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ap_overfill: assert property (wen && full |=> $changed(raddr));
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ap_underfill: assert property (ren && empty |=> $changed(waddr));
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end
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end
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`endif // VERIFIC
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