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More literalincludes
Tidying up of newstart.rst and fifo.sv to include as much code as possible by reference. Should reduce repetition and make it easier if changes occur in source.
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KrystalDelusion
parent
c9fbfa3684
commit
cc27d27c05
3 changed files with 99 additions and 108 deletions
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@ -1,17 +1,14 @@
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// address generator/counter
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module addr_gen (
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input en, clk, rst_n,
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module addr_gen
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#( parameter MAX_DATA=16
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) ( input en, clk, rst_n,
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output reg [3:0] addr
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);
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parameter MAX_DATA = 16;
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initial begin
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addr <= 0;
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end
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initial addr <= 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or negedge rst_n) begin
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always @(posedge clk or negedge rst_n)
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if (~rst_n)
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addr <= 0;
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else if (en)
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@ -19,52 +16,47 @@ module addr_gen (
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule
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// Define our top level fifo entity
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module fifo (
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input wen, ren, clk, rst_n,
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module fifo
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#( parameter MAX_DATA=16
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) ( input wen, ren, clk, rst_n,
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input [7:0] wdata,
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output [7:0] rdata,
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output [4:0] count,
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output full, empty
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);
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parameter MAX_DATA = 16;
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// wire up our sub modules
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wire [3:0] waddr, raddr;
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wire wskip, rskip;
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// fifo storage
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// 8 bit data, fifo depth 16 / 4 bit address
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// reset not defined
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// async read, sync write
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wire [3:0] waddr, raddr;
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reg [7:0] data [MAX_DATA-1:0];
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always @(posedge clk) begin
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always @(posedge clk)
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if (wen)
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data[waddr] <= wdata;
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end
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assign rdata = data[raddr];
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// end storage
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addr_gen #(.MAX_DATA(MAX_DATA)) fifo_writer (
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// addr_gen for both write and read addresses
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_writer (
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.en (wen || wskip),
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.clk (clk ),
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.rst_n (rst_n),
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.addr (waddr)
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);
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addr_gen #(.MAX_DATA(MAX_DATA)) fifo_reader (
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_reader (
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.en (ren || rskip),
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.clk (clk ),
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.rst_n (rst_n),
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.addr (raddr)
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);
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// internals
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// status signals
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reg [4:0] data_count;
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initial begin
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data_count <= 0;
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end
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initial data_count <= 0;
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n)
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@ -79,6 +71,8 @@ module fifo (
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assign empty = (data_count == 0) && rst_n;
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assign count = data_count;
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// overflow protection
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wire wskip, rskip;
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`ifndef NO_FULL_SKIP
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// write while full => overwrite oldest data, move read pointer
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assign rskip = wen && !ren && data_count >= MAX_DATA;
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@ -116,22 +110,22 @@ module fifo (
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a_oflow2: assert (waddr < MAX_DATA);
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// count should be equal to the difference between writer and reader address
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a_count_diff: assert (count == addr_diff
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|| count == MAX_DATA && addr_diff == 0);
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a_count_diff: assert (count == addr_diff
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|| count == MAX_DATA && addr_diff == 0);
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// count should only be able to increase or decrease by 1
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a_counts: assert (count == 0
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|| count == $past(count)
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|| count == $past(count) + 1
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|| count == $past(count) - 1);
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|| count == $past(count)
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|| count == $past(count) + 1
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|| count == $past(count) - 1);
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// read/write addresses can only increase (or stay the same)
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a_raddr: assert (raddr == 0
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|| raddr == $past(raddr)
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|| raddr == $past(raddr + 1));
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a_waddr: assert (waddr == 0
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|| waddr == $past(waddr)
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|| waddr == $past(waddr + 1));
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a_raddr: assert (raddr == 0
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|| raddr == $past(raddr)
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|| raddr == $past(raddr + 1));
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a_waddr: assert (waddr == 0
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|| waddr == $past(waddr)
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|| waddr == $past(waddr + 1));
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// full and empty work as expected
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a_full: assert (!full || full && count == MAX_DATA);
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@ -165,6 +159,7 @@ module fifo (
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ap_waddr3: assert property (!wen && !empty |=> $stable(waddr));
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// can we corrupt our data?
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// these should already be covered by ap_{r,w}addr2
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ap_overfill: assert property (wen && full |=> $changed(raddr));
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ap_underfill: assert property (ren && empty |=> $changed(waddr));
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@ -1,18 +1,15 @@
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// address generator/counter
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module addr_gen (
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input en, clk, rst_n,
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module addr_gen
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#( parameter MAX_DATA=16,
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parameter ADDR_BITS=5
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) ( input en, clk, rst_n,
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output reg [ADDR_BITS-1:0] addr
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);
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parameter MAX_DATA = 16;
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parameter ADDR_BITS = 5;
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initial begin
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addr <= 0;
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end
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initial addr <= 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or negedge rst_n) begin
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always @(posedge clk or negedge rst_n)
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if (~rst_n)
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addr <= 0;
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else if (en)
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@ -20,35 +17,29 @@ module addr_gen (
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule
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// Define our top level fifo entity
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module fifo (
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input wen, ren, clk, rst_n,
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module fifo
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#( parameter MAX_DATA=16,
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parameter ADDR_BITS=5
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) ( input wen, ren, clk, rst_n,
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input [7:0] wdata,
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output [7:0] rdata,
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output [ADDR_BITS:0] count,
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output full, empty
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);
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parameter MAX_DATA = 16;
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parameter ADDR_BITS = 5;
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// wire up our sub modules
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// ADDR_BITS=5 gives 5 bits of address, [4:0]
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// supporting MAX_DATA up to 2**5=32
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wire [ADDR_BITS-1:0] waddr, raddr;
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wire wskip, rskip;
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// fifo storage
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// reset not defined
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// async read, sync write
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wire [3:0] waddr, raddr;
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reg [7:0] data [MAX_DATA-1:0];
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always @(posedge clk) begin
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always @(posedge clk)
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if (wen)
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data[waddr] <= wdata;
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end
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assign rdata = data[raddr];
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// end storage
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// addr_gen for both write and read addresses
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addr_gen #(.MAX_DATA(MAX_DATA), .ADDR_BITS(ADDR_BITS))
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fifo_writer (
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.en (wen || wskip),
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@ -65,11 +56,9 @@ module fifo (
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.addr (raddr)
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);
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// internals
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// status signals
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reg [ADDR_BITS:0] data_count;
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initial begin
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data_count <= 0;
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end
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initial data_count <= 0;
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n)
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@ -84,6 +73,8 @@ module fifo (
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assign empty = (data_count == 0) && rst_n;
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assign count = data_count;
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// overflow protection
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wire wskip, rskip;
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`ifndef NO_FULL_SKIP
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// write while full => overwrite oldest data, move read pointer
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assign rskip = wen && !ren && data_count >= MAX_DATA;
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@ -121,22 +112,22 @@ module fifo (
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a_oflow2: assert (waddr < MAX_DATA);
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// count should be equal to the difference between writer and reader address
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a_count_diff: assert (count == addr_diff
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|| count == MAX_DATA && addr_diff == 0);
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a_count_diff: assert (count == addr_diff
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|| count == MAX_DATA && addr_diff == 0);
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// count should only be able to increase or decrease by 1
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a_counts: assert (count == 0
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|| count == $past(count)
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|| count == $past(count) + 1
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|| count == $past(count) - 1);
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|| count == $past(count)
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|| count == $past(count) + 1
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|| count == $past(count) - 1);
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// read/write addresses can only increase (or stay the same)
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a_raddr: assert (raddr == 0
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|| raddr == $past(raddr)
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|| raddr == $past(raddr + 1));
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a_waddr: assert (waddr == 0
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|| waddr == $past(waddr)
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|| waddr == $past(waddr + 1));
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a_raddr: assert (raddr == 0
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|| raddr == $past(raddr)
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|| raddr == $past(raddr + 1));
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a_waddr: assert (waddr == 0
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|| waddr == $past(waddr)
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|| waddr == $past(waddr + 1));
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// full and empty work as expected
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a_full: assert (!full || full && count == MAX_DATA);
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