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Update examples

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-29 19:32:03 +02:00
parent 2fa29974dd
commit c5e5f5dcbb
9 changed files with 51 additions and 46 deletions
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4
docs/examples/puzzles/primegen.sby
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@ -12,10 +12,10 @@ primes_fail: expect fail
smtbmc --dumpsmt2 --progress --stbv z3
[script]
read_verilog -formal primegen.v
read -formal primegen.sv
primes_fail: chparam -set offset 7 primes
primegen: prep -top primegen
~primegen: prep -top primes
[files]
primegen.v
primegen.sv

27
docs/examples/puzzles/primegen.sv Normal file
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@ -0,0 +1,27 @@
module primegen;
(* anyconst *) reg [31:0] prime;
(* allconst *) reg [15:0] factor;
always @* begin
if (1 < factor && factor < prime)
assume ((prime % factor) != 0);
assume (prime > 1000000000);
cover (1);
end
endmodule
module primes;
parameter [8:0] offset = 500;
(* anyconst *) reg [8:0] prime1;
wire [9:0] prime2 = prime1 + offset;
(* allconst *) reg [4:0] factor;
always @* begin
if (1 < factor && factor < prime1)
assume ((prime1 % factor) != 0);
if (1 < factor && factor < prime2)
assume ((prime2 % factor) != 0);
assume (1 < prime1);
cover (1);
end
endmodule

27
docs/examples/puzzles/primegen.v
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@ -1,27 +0,0 @@
module primegen;
wire [31:0] prime = $anyconst;
wire [15:0] factor = $allconst;
always @* begin
if (1 < factor && factor < prime)
assume((prime % factor) != 0);
assume(prime > 1000000000);
cover(1);
end
endmodule
module primes;
parameter [8:0] offset = 500;
wire [8:0] prime1 = $anyconst;
wire [9:0] prime2 = prime1 + offset;
wire [4:0] factor = $allconst;
always @* begin
if (1 < factor && factor < prime1)
assume((prime1 % factor) != 0);
if (1 < factor && factor < prime2)
assume((prime2 % factor) != 0);
assume(1 < prime1);
cover(1);
end
endmodule

4
docs/examples/puzzles/wolf_goat_cabbage.sby
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@ -6,8 +6,8 @@ depth 100
smtbmc
[script]
read_verilog -formal wolf_goat_cabbage.v
read -formal wolf_goat_cabbage.sv
prep -top wolf_goat_cabbage
[files]
wolf_goat_cabbage.v
wolf_goat_cabbage.sv

8
docs/examples/puzzles/wolf_goat_cabbage.v → docs/examples/puzzles/wolf_goat_cabbage.sv
View file

@ -14,19 +14,19 @@ module wolf_goat_cabbage (input clk, input w, g, c);
always @(posedge clk) begin
// maximum one of the control signals must be high
assume(w+g+c <= 1);
assume (w+g+c <= 1);
// we want wolf, goat, and cabbage on the 2nd river bank
cover(bank_w && bank_g && bank_c);
cover (bank_w && bank_g && bank_c);
// don't leave wolf and goat unattended
if (bank_w != bank_m) begin
assume(bank_w != bank_g);
assume (bank_w != bank_g);
end
// don't leave goat and cabbage unattended
if (bank_g != bank_m) begin
assume(bank_g != bank_c);
assume (bank_g != bank_c);
end
// man travels and takes the selected item with him