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Update examples

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-29 19:32:03 +02:00
parent 2fa29974dd
commit c5e5f5dcbb
9 changed files with 51 additions and 46 deletions
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4
docs/examples/multiclk/dpmem.sby
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@ -7,8 +7,8 @@ multiclock on
smtbmc
[script]
read_verilog -sv -formal dpmem.sv
prep -nordff -top top
read -formal dpmem.sv
prep -top top
chformal -early -assume
[files]

15
docs/examples/multiclk/dpmem.sv
View file

@ -41,14 +41,17 @@ module top (
reg shadow_valid = 0;
reg [3:0] shadow_data;
const rand reg [3:0] shadow_addr;
(* anyconst *) reg [3:0] shadow_addr;
always @($global_clock) begin
assume($stable(rc) || $stable(wc));
reg init = 1;
(* gclk *) reg gclk;
if (!$initstate) begin
always @(posedge gclk) begin
assume ($stable(rc) || $stable(wc));
if (!init) begin
if ($rose(rc) && shadow_valid && shadow_addr == $past(ra)) begin
assert(shadow_data == rd);
assert (shadow_data == rd);
end
if ($rose(wc) && $past(we) && shadow_addr == $past(wa)) begin
@ -56,5 +59,7 @@ module top (
shadow_valid <= 1;
end
end
init <= 0;
end
endmodule