Update examples

Signed-off-by: Clifford Wolf <clifford@clifford.at>

docs/examples/demos/fib.sby

@@ -21,8 +21,8 @@ aiger suprove
 --
 
 [script]
-read_verilog -formal fib.v
+read -formal fib.sv
 prep -top fib
 
 [files]
-fib.v
+fib.sv

docs/examples/demos/fib.sv

@@ -54,10 +54,10 @@ module fib (
 			cover ($past(n) == 15);
 		end
 
-		assume (s_eventually !pause);
+		assume property (s_eventually !pause);
 
 		if (start && !pause)
-			assert (s_eventually done);
+			assert property (s_eventually done);
 	end
 `endif
 endmodule