Rename SymbiYosys to SBY

COPYING

@@ -1,4 +1,4 @@
-SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+SBY -- Front-end for Yosys-based formal verification flows
 
 Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 

Makefile

@@ -21,7 +21,7 @@ endif
 help:
 	@echo ""
 	@echo "sudo make install"
-	@echo "    build and install SymbiYosys (sby)"
+	@echo "    build and install SBY"
 	@echo ""
 	@echo "make html"
 	@echo "    build documentation in docs/build/html/"

README.md

@@ -1,10 +1,10 @@
-SymbiYosys (sby) is a front-end driver program for [Yosys](https://yosyshq.net/yosys/)-based formal hardware verification flows. See [https://yosyshq.readthedocs.io/projects/sby/](https://yosyshq.readthedocs.io/projects/sby/) for documentation on how to use SymbiYosys.
+SBY is a front-end driver program for [Yosys](https://yosyshq.net/yosys/)-based formal hardware verification flows. See [https://yosyshq.readthedocs.io/projects/sby/](https://yosyshq.readthedocs.io/projects/sby/) for documentation on how to use SBY.
 
-SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the ["Selecting the right engine" section of the documentation](https://yosyshq.readthedocs.io/projects/sby/en/latest/quickstart.html#selecting-the-right-engine).
+SBY itself is licensed under the ISC license, note that the solvers and other components used by SBY come with their own license terms. There is some more details in the ["Selecting the right engine" section of the documentation](https://yosyshq.readthedocs.io/projects/sby/en/latest/quickstart.html#selecting-the-right-engine).
 
 ---
 
-SymbiYosys (sby) is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.
+SBY is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.
 
 * [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link
 * OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite

docs/Makefile

@@ -91,9 +91,9 @@ qthelp:
 	@echo
 	@echo "Build finished; now you can run "qcollectiongenerator" with the" \
 	      ".qhcp project file in $(BUILDDIR)/qthelp, like this:"
-	@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/SymbiYosys.qhcp"
+	@echo "# qcollectiongenerator $(BUILDDIR)/qthelp/SBY.qhcp"
 	@echo "To view the help file:"
-	@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/SymbiYosys.qhc"
+	@echo "# assistant -collectionFile $(BUILDDIR)/qthelp/SBY.qhc"
 
 .PHONY: applehelp
 applehelp:
@@ -110,8 +110,8 @@ devhelp:
 	@echo
 	@echo "Build finished."
 	@echo "To view the help file:"
-	@echo "# mkdir -p $$HOME/.local/share/devhelp/SymbiYosys"
-	@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/SymbiYosys"
+	@echo "# mkdir -p $$HOME/.local/share/devhelp/SBY"
+	@echo "# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/SBY"
 	@echo "# devhelp"
 
 .PHONY: epub

docs/source/index.rst

@@ -1,9 +1,9 @@
 
-SymbiYosys (sby) Documentation
+SBY Documentation
 ==============================
 
-SymbiYosys (sby) is a front-end driver program for Yosys-based formal
-hardware verification flows. SymbiYosys provides flows for the following
+SBY is a front-end driver program for Yosys-based formal
+hardware verification flows. SBY provides flows for the following
 formal tasks:
 
    * Bounded verification of safety properties (assertions)

docs/source/install.rst

@@ -8,7 +8,7 @@ This document will guide you through the process of installing sby.
 CAD suite(s)
 ************
 
-Sby (SymbiYosys) is part of the `Tabby CAD Suite
+Sby (SBY) is part of the `Tabby CAD Suite
 <https://www.yosyshq.com/tabby-cad-datasheet>`_ and the `OSS CAD Suite
 <https://github.com/YosysHQ/oss-cad-suite-build>`_! The easiest way to use sby
 is to install the binary software suite, which contains all required

docs/source/license.rst

@@ -1,12 +1,12 @@
 
-SymbiYosys license
+SBY license
 ==================
 
-SymbiYosys (sby) itself is licensed under the ISC license:
+SBY itself is licensed under the ISC license:
 
 .. code-block:: text
 
-   SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+   SBY -- Front-end for Yosys-based formal verification flows
    
    Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
    
@@ -22,6 +22,6 @@ SymbiYosys (sby) itself is licensed under the ISC license:
    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-Note that the solvers and other components used by SymbiYosys come with their
+Note that the solvers and other components used by SBY come with their
 own license terms.
 

docs/source/quickstart.rst

@@ -99,10 +99,10 @@ difference in addresses, and then compare with the count signal.
    :end-at: ;
    :dedent:
 
-SymbiYosys
+SBY
 **********
 
-SymbiYosys (sby) uses a .sby file to define a set of tasks used for
+SBY uses a .sby file to define a set of tasks used for
 verification.  
 
 **basic**

docs/source/verilog.rst

@@ -3,7 +3,7 @@ Formal extensions to Verilog
 ============================
 
 Any Verilog file may be read using ``read -formal <file>`` within the
-SymbiYosys ``script`` section.  Multiple files may be given on the sames
+SBY ``script`` section.  Multiple files may be given on the sames
 line, or various files may be read in subsequent lines.
 
 ``read -formal`` will also define the ``FORMAL`` macro, which can be used
@@ -28,7 +28,7 @@ example above. Refer to :doc:`verific` for more on the Verific front end.
 SystemVerilog Immediate Assertions
 ----------------------------------
 
-SymbiYosys supports three basic immediate assertion types.
+SBY supports three basic immediate assertion types.
 
 1. ``assume(<expr>);``
 
@@ -39,15 +39,15 @@ SymbiYosys supports three basic immediate assertion types.
 2. ``assert(<expr>);``
 
    An assertion is something the solver will try to make false.  Any time
-   SymbiYosys is run with ``mode bmc``, the proof will fail if some set
+   SBY is run with ``mode bmc``, the proof will fail if some set
    of inputs can cause the ``<expr>`` within the assertion to be zero (false).
-   When SymbiYosys is run with ``mode prove``, the proof may also yield an
+   When SBY is run with ``mode prove``, the proof may also yield an
    ``UNKNOWN`` result if an assertion can be made to fail during the induction
    step.
 
 3. ``cover(<expr>);``
 
-   A cover statement only applies when SymbiYosys is ran with option
+   A cover statement only applies when SBY is ran with option
    ``mode cover``.  In this case, the formal solver will start at the
    beginning of time (i.e. when all initial statements are true), and it will
    try to find some clock when ``<expr>`` can be made to be true.  Such a

sbysrc/sby.py

@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_autotune.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
 #

sbysrc/sby_core.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_design.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2022  N. Engelhardt <nak@yosyshq.com>
 #

sbysrc/sby_engine_abc.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_engine_aiger.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_engine_btor.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_engine_smtbmc.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_jobserver.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
 #

sbysrc/sby_mode_bmc.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_mode_cover.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_mode_live.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_mode_prove.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2016  Claire Xenia Wolf <claire@yosyshq.com>
 #

sbysrc/sby_sim.py

@@ -1,5 +1,5 @@
 #
-# SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
+# SBY -- Front-end for Yosys-based formal verification flows
 #
 # Copyright (C) 2022  Jannis Harder <jix@yosyshq.com> <me@jix.one>
 #