mirror of
https://github.com/YosysHQ/sby.git
synced 2025-12-01 19:19:07 +00:00
Fix typo on anyconst attribute in verilog.rst
This commit is contained in:
parent
87825b8b50
commit
af160ada0f
1 changed files with 1 additions and 1 deletions
|
|
@ -167,7 +167,7 @@ time, as in
|
||||||
|
|
||||||
.. code-block:: systemverilog
|
.. code-block:: systemverilog
|
||||||
|
|
||||||
(* anyconst ) reg some_value;
|
(* anyconst *) reg some_value;
|
||||||
|
|
||||||
The ``(* anyconst *)`` attribute will create a solver chosen constant.
|
The ``(* anyconst *)`` attribute will create a solver chosen constant.
|
||||||
It is often used when verifying memories: the proof allows the solver to
|
It is often used when verifying memories: the proof allows the solver to
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue