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Add init check
Prevent rst_n from going low once it has gone high.
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@ -69,6 +69,15 @@ module fifo (
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? waddr - raddr
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? waddr - raddr
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: waddr + MAX_DATA - raddr;
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: waddr + MAX_DATA - raddr;
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reg init = 0;
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always @(posedge clk) begin
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if (rst_n)
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init <= 1;
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// if init is low we don't care about the value of rst_n
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// if init is high (rst_n has ben high), then rst_n must remain high
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assume (!init || init && rst_n);
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end
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// tests
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// tests
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst_n) begin
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if (rst_n) begin
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