Add more documentation

Signed-off-by: Clifford Wolf <clifford@clifford.at>

docs/source/verilog.rst

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+
+Formal extensions to Verilog
+============================
+
+TBD
+
+``read_verilog -formal``
+
+SystemVerilog Immediate Assertions
+----------------------------------
+
+TBD
+
+``assert(<expr>);``
+
+``assume(<expr>);``
+
+``cover(<expr>);``
+
+SystemVerilog Functions
+-----------------------
+
+TBD
+
+``$past``
+
+``$stable``
+
+``$rose``, ``$fell``
+
+Liveness and Fairness
+---------------------
+
+TBD
+
+``assert(eventually <expr>);``
+
+``assume(eventually <expr>);``
+
+Unconstrained Variables
+-----------------------
+
+TBD
+
+Nonstandard Extensions in Yosys
+-------------------------------
+
+TBD
+