mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-12-09 23:03:37 +00:00
Code Activity

add new blackbox test cases

Browse source
This commit is contained in:
Emily Schmidt 2025-04-08 13:47:59 +01:00
parent 9675d158ce
commit 8423d3e2c8
5 changed files with 172 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

31
tests/unsorted/blackbox.sby
View file

@ -1,31 +0,0 @@
[options]
mode bmc
depth 1
expect error
[engines]
smtbmc
[script]
read_verilog -formal test.v
prep -top top
[file test.v]
(* blackbox *)
module submod(a, b);
input [7:0] a;
output [7:0] b;
endmodule
module top;
wire [7:0] a = $anyconst, b;
submod submod(
.a(a),
.b(b)
);
always @* begin
assert(~a == b);
end
endmodule