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Add tbtop config option

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Clifford Wolf 2017-07-01 18:33:36 +02:00
parent 3fb72628de
commit 6ef12a4b31
5 changed files with 19 additions and 6 deletions
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docs/source/reference.rst
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@ -45,6 +45,9 @@ options are:
| | | to counter example traces. Use ``none`` to disable |
| | | conversion of AIGER witnesses. Default: ``yices`` |
+-------------+------------+---------------------------------------------------------+
| ``tbtop`` | All | The top module for generated Verilog test benches, as |
| | | hierarchical path relative to the design top module. |
+-------------+------------+---------------------------------------------------------+
| ``smtc`` | ``bmc``, | Pass this ``.smtc`` file to the smtbmc engine. All |
| | ``prove``, | other engines are disabled when this option is used. |
| | ``cover`` | Default: None |