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Unified trace generation using yosys's sim across all engines

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Currently opt-in using the `fst` or `vcd_sim` options.
This commit is contained in:
Jannis Harder 2023-01-10 15:33:18 +01:00
parent 4c44a10f72
commit 6d3b5aa960
15 changed files with 686 additions and 183 deletions
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2
tests/keepgoing/keepgoing_same_step.py
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@ -9,7 +9,7 @@ assert_not_a = line_ref(workdir, src, "assert(!a)")
assert_0 = line_ref(workdir, src, "assert(0)")
log = open(workdir + "/logfile.txt").read()
log_per_trace = log.split("Writing trace to VCD file")[:-1]
log_per_trace = log.split("Writing trace to Yosys witness file")[:-1]
assert len(log_per_trace) == 2