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Unified trace generation using yosys's sim across all engines

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Currently opt-in using the `fst` or `vcd_sim` options.
This commit is contained in:
Jannis Harder 2023-01-10 15:33:18 +01:00
parent 4c44a10f72
commit 6d3b5aa960
15 changed files with 686 additions and 183 deletions
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4
tests/keepgoing/keepgoing_multi_step.py
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@ -11,7 +11,7 @@ step_5 = line_ref(workdir, src, "step 5")
step_7 = line_ref(workdir, src, "step 7")
log = open(workdir + "/logfile.txt").read()
log_per_trace = log.split("Writing trace to VCD file")[:-1]
log_per_trace = log.split("Writing trace to Yosys witness file")[:-1]
assert len(log_per_trace) == 4
@ -27,5 +27,5 @@ assert re.search(r"Assert failed in test: %s \(.*\)$" % step_5, log_per_trace[2]
assert re.search(r"Assert failed in test: %s \(.*\) \[failed before\]$" % step_3_7, log_per_trace[3], re.M)
assert re.search(r"Assert failed in test: %s \(.*\)$" % step_7, log_per_trace[3], re.M)
pattern = f"Property ASSERT in test at {assert_0} failed. Trace file: engine_0/trace0.vcd"
pattern = f"Property ASSERT in test at {assert_0} failed. Trace file: engine_0/trace0.(vcd|fst)"
assert re.search(pattern, open(f"{workdir}/{workdir}.xml").read())