Unified trace generation using yosys's sim across all engines

Currently opt-in using the `fst` or `vcd_sim` options.

tests/keepgoing/keepgoing_multi_step.py

@@ -11,7 +11,7 @@ step_5 = line_ref(workdir, src, "step 5")
 step_7 = line_ref(workdir, src, "step 7")
 
 log = open(workdir + "/logfile.txt").read()
-log_per_trace = log.split("Writing trace to VCD file")[:-1]
+log_per_trace = log.split("Writing trace to Yosys witness file")[:-1]
 
 assert len(log_per_trace) == 4
 
@@ -27,5 +27,5 @@ assert re.search(r"Assert failed in test: %s \(.*\)$" % step_5, log_per_trace[2]
 assert re.search(r"Assert failed in test: %s \(.*\) \[failed before\]$" % step_3_7, log_per_trace[3], re.M)
 assert re.search(r"Assert failed in test: %s \(.*\)$" % step_7, log_per_trace[3], re.M)
 
-pattern = f"Property ASSERT in test at {assert_0} failed. Trace file: engine_0/trace0.vcd"
+pattern = f"Property ASSERT in test at {assert_0} failed. Trace file: engine_0/trace0.(vcd|fst)"
 assert re.search(pattern, open(f"{workdir}/{workdir}.xml").read())

tests/keepgoing/keepgoing_same_step.py

@@ -9,7 +9,7 @@ assert_not_a = line_ref(workdir, src, "assert(!a)")
 assert_0 = line_ref(workdir, src, "assert(0)")
 
 log = open(workdir + "/logfile.txt").read()
-log_per_trace = log.split("Writing trace to VCD file")[:-1]
+log_per_trace = log.split("Writing trace to Yosys witness file")[:-1]
 
 assert len(log_per_trace) == 2
 

tests/keepgoing/keepgoing_smtc.py

@@ -12,7 +12,7 @@ assert_false = line_ref(workdir, "extra.smtc", "assert false")
 assert_distinct = line_ref(workdir, "extra.smtc", "assert (distinct")
 
 log = open(workdir + "/logfile.txt").read()
-log_per_trace = log.split("Writing trace to VCD file")[:-1]
+log_per_trace = log.split("Writing trace to Yosys witness file")[:-1]
 
 assert len(log_per_trace) == 4
 

tests/unsorted/btor_meminit.sby

@@ -0,0 +1,48 @@
+[tasks]
+btormc
+#pono
+smtbmc
+
+[options]
+mode bmc
+expect fail
+
+[engines]
+btormc: btor btormc
+# pono: btor pono
+smtbmc: smtbmc
+
+[script]
+read -formal top.sv
+prep -top top -flatten
+
+[file top.sv]
+
+module top(input clk);
+
+    inner inner(clk);
+
+endmodule
+
+module inner(input clk);
+    reg [7:0] counter = 0;
+
+    reg [1:0] mem [0:255];
+
+    initial begin
+        mem[0] = 0;
+        mem[1] = 1;
+        mem[2] = 2;
+        mem[3] = 2;
+        mem[4] = 0;
+        mem[7] = 0;
+    end
+
+    always @(posedge clk) begin
+        counter <= counter + 1;
+        foo: assert (mem[counter] < 3);
+        bar: assume (counter < 7);
+
+        mem[counter] <= 0;
+    end
+endmodule

tests/unsorted/cover_unreachable.sby

@@ -0,0 +1,34 @@
+[tasks]
+btormc
+smtbmc
+
+[options]
+mode cover
+expect fail
+
+[engines]
+btormc: btor btormc
+smtbmc: smtbmc
+
+[script]
+read -formal top.sv
+prep -top top -flatten
+
+[file top.sv]
+
+module top(input clk);
+
+    inner inner(clk);
+
+endmodule
+
+module inner(input clk);
+    reg [7:0] counter = 0;
+
+    always @(posedge clk) begin
+        counter <= counter == 4 ? 0 : counter + 1;
+
+        reachable: cover (counter == 3);
+        unreachable: cover (counter == 5);
+    end
+endmodule