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Unified trace generation using yosys's sim across all engines

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Currently opt-in using the `fst` or `vcd_sim` options.
This commit is contained in:
Jannis Harder 2023-01-10 15:33:18 +01:00
parent 4c44a10f72
commit 6d3b5aa960
15 changed files with 686 additions and 183 deletions
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1
sbysrc/sby_mode_cover.py
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@ -21,7 +21,6 @@ from sby_core import SbyProc
def run(task):
task.handle_int_option("depth", 20)
task.handle_int_option("append", 0)
for engine_idx, engine in task.engine_list():
task.log(f"{click.style(f'engine_{engine_idx}', fg='magenta')}: {' '.join(engine)}")