mirror of
https://github.com/YosysHQ/sby.git
synced 2025-08-08 22:31:26 +00:00
Unified trace generation using yosys's sim across all engines
Currently opt-in using the `fst` or `vcd_sim` options.
This commit is contained in:
Jannis Harder
parent
4c44a10f72
commit
6d3b5aa960
15 changed files with 686 additions and 183 deletions
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@ -16,8 +16,9 @@
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import re, os, getopt, click
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import re, os, getopt, click, glob
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from sby_core import SbyProc
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from sby_sim import sim_witness_trace
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def run(mode, task, engine_idx, engine):
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smtbmc_opts = []
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@ -141,20 +142,37 @@ def run(mode, task, engine_idx, engine):
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if not progress:
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smtbmc_opts.append("--noprogress")
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if task.opt_skip is not None:
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t_opt = "{}:{}".format(task.opt_skip, task.opt_depth)
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else:
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t_opt = "{}".format(task.opt_depth)
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smtbmc_vcd = task.opt_vcd and not task.opt_vcd_sim
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smtbmc_append = 0
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sim_append = 0
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log = task.log_prefix(f"engine_{engine_idx}")
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if task.opt_append_assume:
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smtbmc_append = task.opt_append
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elif smtbmc_vcd:
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if not task.opt_append_assume:
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log("For VCDs generated by smtbmc the option 'append_assume off' is ignored")
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smtbmc_append = task.opt_append
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else:
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sim_append = task.opt_append
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trace_ext = 'fst' if task.opt_fst else 'vcd'
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random_seed = f"--info \"(set-option :random-seed {random_seed})\"" if random_seed else ""
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dump_flags = f"--dump-vcd {trace_prefix}.vcd " if task.opt_vcd else ""
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dump_flags = f"--dump-vcd {trace_prefix}.vcd " if smtbmc_vcd else ""
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dump_flags += f"--dump-yw {trace_prefix}.yw --dump-vlogtb {trace_prefix}_tb.v --dump-smtc {trace_prefix}.smtc"
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proc = SbyProc(
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task,
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procname,
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task.model(model_name),
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f"""cd {task.workdir}; {task.exe_paths["smtbmc"]} {" ".join(smtbmc_opts)} -t {t_opt} {random_seed} --append {task.opt_append} {dump_flags} model/design_{model_name}.smt2""",
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f"""cd {task.workdir}; {task.exe_paths["smtbmc"]} {" ".join(smtbmc_opts)} -t {t_opt} {random_seed} --append {smtbmc_append} {dump_flags} model/design_{model_name}.smt2""",
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logfile=open(logfile_prefix + ".txt", "w"),
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logstderr=(not progress)
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)
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@ -167,12 +185,30 @@ def run(mode, task, engine_idx, engine):
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proc_status = None
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last_prop = []
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pending_sim = None
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current_step = None
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procs_running = 1
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def output_callback(line):
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nonlocal proc_status
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nonlocal last_prop
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nonlocal pending_sim
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nonlocal current_step
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nonlocal procs_running
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if pending_sim:
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sim_proc = sim_witness_trace(procname, task, engine_idx, pending_sim, append=sim_append)
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sim_proc.register_exit_callback(simple_exit_callback)
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procs_running += 1
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pending_sim = None
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smt2_trans = {'\\':'/', '|':'/'}
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match = re.match(r"^## [0-9: ]+ .* in step ([0-9]+)\.\.", line)
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if match:
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current_step = int(match[1])
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return line
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match = re.match(r"^## [0-9: ]+ Status: FAILED", line)
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if match:
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proc_status = "FAIL"
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@ -193,31 +229,45 @@ def run(mode, task, engine_idx, engine):
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proc_status = "ERROR"
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return line
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match = re.match(r"^## [0-9: ]+ Assert failed in (\S+): (\S+) \((\S+)\)", line)
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match = re.match(r"^## [0-9: ]+ Assert failed in (\S+): (\S+)(?: \((\S+)\))?", line)
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if match:
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cell_name = match[3]
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cell_name = match[3] or match[2]
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop.status = "FAIL"
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last_prop.append(prop)
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return line
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match = re.match(r"^## [0-9: ]+ Reached cover statement at (\S+) \((\S+)\) in step \d+.", line)
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match = re.match(r"^## [0-9: ]+ Reached cover statement at (\S+)(?: \((\S+)\))? in step \d+\.", line)
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if match:
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cell_name = match[2]
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cell_name = match[2] or match[1]
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop.status = "PASS"
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last_prop.append(prop)
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return line
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match = re.match(r"^## [0-9: ]+ Writing trace to VCD file: (\S+)", line)
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if match and last_prop:
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for p in last_prop:
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if not p.tracefile:
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p.tracefile = match[1]
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last_prop = []
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return line
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if smtbmc_vcd and not task.opt_fst:
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match = re.match(r"^## [0-9: ]+ Writing trace to VCD file: (\S+)", line)
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if match:
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tracefile = match[1]
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trace = os.path.basename(tracefile)[:-4]
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engine_case = mode.split('_')[1] if '_' in mode else None
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task.summary.add_event(engine_idx=engine_idx, trace=trace, path=tracefile, engine_case=engine_case)
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match = re.match(r"^## [0-9: ]+ Unreached cover statement at (\S+) \((\S+)\).", line)
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if match and last_prop:
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for p in last_prop:
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task.summary.add_event(
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engine_idx=engine_idx, trace=trace,
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type=p.celltype, hdlname=p.hdlname, src=p.location, step=current_step)
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p.tracefiles.append(tracefile)
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last_prop = []
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return line
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else:
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match = re.match(r"^## [0-9: ]+ Writing trace to Yosys witness file: (\S+)", line)
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if match:
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tracefile = match[1]
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pending_sim = tracefile
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match = re.match(r"^## [0-9: ]+ Unreached cover statement at (\S+) \((\S+)\)\.", line)
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if match:
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cell_name = match[2]
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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@ -225,43 +275,28 @@ def run(mode, task, engine_idx, engine):
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return line
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def simple_exit_callback(retcode):
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nonlocal procs_running
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procs_running -= 1
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if not procs_running:
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last_exit_callback()
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def exit_callback(retcode):
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if proc_status is None:
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task.error(f"engine_{engine_idx}: Engine terminated without status.")
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simple_exit_callback(retcode)
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def last_exit_callback():
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if mode == "bmc" or mode == "cover":
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task.update_status(proc_status)
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proc_status_lower = proc_status.lower() if proc_status == "PASS" else proc_status
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task.log(f"{click.style(f'engine_{engine_idx}', fg='magenta')}: Status returned by engine: {proc_status_lower}")
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task.summary.append(f"""engine_{engine_idx} ({" ".join(engine)}) returned {proc_status_lower}""")
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if proc_status == "FAIL" and mode != "cover":
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if os.path.exists(f"{task.workdir}/engine_{engine_idx}/trace.vcd"):
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task.summary.append(f"counterexample trace: {task.workdir}/engine_{engine_idx}/trace.vcd")
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elif proc_status == "PASS" and mode == "cover":
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print_traces_max = 5
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for i in range(print_traces_max):
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if os.path.exists(f"{task.workdir}/engine_{engine_idx}/trace{i}.vcd"):
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task.summary.append(f"trace: {task.workdir}/engine_{engine_idx}/trace{i}.vcd")
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else:
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break
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else:
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excess_traces = 0
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while os.path.exists(f"{task.workdir}/engine_{engine_idx}/trace{print_traces_max + excess_traces}.vcd"):
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excess_traces += 1
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if excess_traces > 0:
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task.summary.append(f"""and {excess_traces} further trace{"s" if excess_traces > 1 else ""}""")
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elif proc_status == "PASS" and mode == "bmc":
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for prop in task.design.hierarchy:
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if prop.type == prop.Type.ASSERT and prop.status == "UNKNOWN":
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prop.status = "PASS"
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task.summary.set_engine_status(engine_idx, proc_status_lower)
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task.terminate()
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elif mode in ["prove_basecase", "prove_induction"]:
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proc_status_lower = proc_status.lower() if proc_status == "PASS" else proc_status
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task.log(f"""{click.style(f'engine_{engine_idx}', fg='magenta')}: Status returned by engine for {mode.split("_")[1]}: {proc_status_lower}""")
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task.summary.append(f"""engine_{engine_idx} ({" ".join(engine)}) returned {proc_status_lower} for {mode.split("_")[1]}""")
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task.summary.set_engine_status(engine_idx, proc_status_lower, mode.split("_")[1])
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if mode == "prove_basecase":
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for proc in task.basecase_procs:
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@ -272,8 +307,6 @@ def run(mode, task, engine_idx, engine):
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else:
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task.update_status(proc_status)
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if os.path.exists(f"{task.workdir}/engine_{engine_idx}/trace.vcd"):
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task.summary.append(f"counterexample trace: {task.workdir}/engine_{engine_idx}/trace.vcd")
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task.terminate()
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elif mode == "prove_induction":
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@ -287,9 +320,6 @@ def run(mode, task, engine_idx, engine):
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assert False
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if task.basecase_pass and task.induction_pass:
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for prop in task.design.hierarchy:
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if prop.type == prop.Type.ASSERT and prop.status == "UNKNOWN":
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prop.status = "PASS"
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task.update_status("PASS")
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task.summary.append("successful proof by k-induction.")
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task.terminate()
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@ -298,4 +328,4 @@ def run(mode, task, engine_idx, engine):
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assert False
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proc.output_callback = output_callback
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proc.exit_callback = exit_callback
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proc.register_exit_callback(exit_callback)
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